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RISCV CPU Verification – Opportunities and Challenges

Conference: Verification Futures 2023 (click here to see full programme)
Speaker: Divyang Agrawal
Presentation Title: RISCV CPU Verification - Opportunities and Challenges

The highly configurable nature of RISCV ISA makes it uniquely suited for a hierarchical verification methodology covering both architectural and microarchitectural complexity. This technical talk will focus on how Tenstorrent leveraged on the lessons from x86 and ARM to build a modular and scalable CPU verification framework. It will also preview how design complexity has to be tackled looking at silicon as a starting point. And ultimately why robust open source RISCV verification collateral is essential for broader adoption of the ISA from microcontrollers to high performance datacenter class products

Speaker Bio:

Divyang Agrawal is a Senior Director at Tenstorrent where he works on RISCV Cores focusing on design verification, emulation, architectural tools and methodologies. He has previously worked on x86 and ARM architectures. Prior to Tenstorrent, Divyang worked at AMD where he held leadership roles within AMD's CPU Cores team working on several generations of high-performance cores. He also led the CPU Power Management IPs and Silicon Validation for all AMD cores. Divyang has a BTech in EE from Nagpur, India and an MBA from University of California at Berkeley

Key Points:
  • What can RISCV verification learn from decades of effort on x86 and ARM verification
  • The open nature of RISCV ISA offers tremendous opportunities and interesting challenges. Can we meet some of these by collaboration across the open source community
  • DV complexity can leverage on ISA flexibility
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