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A Modern Fable: The Lost Art of Processor Verification

Conference: Verification Futures 2023 (click here to see full programme)
Speaker: Larry Lapides
Presentation Title: A Modern Fable: The Lost Art of Processor Verification

The open standard Instruction Set Architecture (ISA) of RISC-V offers new design flexibilities and opportunities, and is having a significant impact on the design side of many SoC projects. An optimized processor enables developers to unlock hidden value in performance, power savings, security, differentiated features, and an enduring market advantage.

While every SoC design team now has a free architecture license to build a custom RISC-V processor or extend an existing core with custom instructions, this also represents a surge in verification work and a step-change in verification complexity. With other ISAs, verification methodologies have largely been kept proprietary. Now within the RISC-V community, the art and science of processor verification is resurfacing. This represents a massive migration in verification responsibility, and the creation of a new verification ecosystem.

This talk outlines the various methodologies for RISC-V processor verification, which leverage established SoC verification technologies with UVM and SystemVerilog. The individual components of a step-compare methodology will be discussed, including reference model, verification IP, functional coverage and test generation. Detailed examples of successful, complex processor verification projects will be presented, including flows to support verification of complex events and architectures such as interrupts, Debug and privilege modes, multi-hart processors and multi-issue and out-of-order pipelines.

Speaker Bio:

Larry is currently VP Worldwide Sales at Imperas Software Ltd., and previously ran worldwide sales at EDA companies including Verisity Design (the top performing IPO of 2001 in the U.S.). Larry has about 30 years in software tools and EDA, plus time spent in infrared sensors and systems engineering. Larry holds a BA in Physics from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University where he was an Entrepreneur-in-Residence during Fall 2006, when he developed and taught the course on Entrepreneurial Communication and Influence.

Key Points:
  • RISC-V is inevitable; everyone will be using RISC-V processors 2-3 years from now
  • RISC-V processor verification is key to the success of RISC-V based SoCs
  • Processor verification is a significant increase in verification complexity
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