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Verification Makeover with RISC-V Processor Designs

Conference: Verification Futures 2023 (click here to see full programme)
Speaker: Lavanya J
Presentation Title: Verification Makeover with RISC-V Processor Designs
Abstract: In order to meet the quality of the growing RISC-V business in domains ranging from low power to high performance compute, high quality rapid verification flow is the need of the hour. It is imperative we replicate the open standard of the ISA to its important ecosystem enabler like the verification infrastructure and methodology. The RISC-V era inspires the verification community to step up and do a makeover interms of adapting software infrastructure best practises and propose a new open verification standard for processor verification
Speaker Bio: Lavanya J is the founder and the CEO of Vyoma Systems deliverying Verification-As-A-Service platform for the next generation processor verification demands. After her MS from Department of Computer Science,IIT Madras, she has a 12+ years of experience working with various processor and system verification teams in both industry (IBM, ARM,Rambus) and academia (SHAKTI RISC-V Ecosystem, IIT Madras).
Key Points:
  • RISC-V Processor verification has an opportunity to adopt the emerging software technology trends.
  • The Python based UVM methodology can be leveraged for the rich ecosystem it provides for verification innovation.
  • Verification is the DevSecOps platform for processor designs.
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