Verification Futures Conference 2023 UK

The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.

Event at a Glance

Thursday, 22 June 2023 – Full day conference, exhibition and networking event

Reading (UK) and online

FREE to attend conference In-Person or Online


Call for Submissions

Abstracts are now being invited for talks at VF2023. Talks on a wide range of topical verification issues are invited, including, but not limited to; artificial intelligence and machine learning in verification, safety, security, software testing, and of course hardware verification.

Please visit VF2023 for guidance on the types of presentations that we are looking for.

Conference Program – Provisional

08:30 Arrival: Breakfast and Networking Slides Videos
09:25 Welcome: Mike Bartley, Tessolve Semiconductor Ltd
Keynote Speakers
09:30 Speaker Name, Company Name
User Top Verification Challenges
10:00 Challenge Speaker 1
10:20 Challenge Speaker 2
10:30 Speaker Name (Cadence) Platinum Sponsor
11:00 Refreshments and Networking
Multi-Track Session (AM)
Track 1 – User presentations on Verification Formal

The Power of Formal Verification: From flops to billion-gate designs

Dr Ashish Darbari (Axiomise)


Automatic Software Formal Verification

Nick Tudor (D-RisQ Ltd)

12:10 Session 1 – Speaker 3
Track 2 – Student Session 1

Introduction to Verification and SystemVerilog for Beginners

Dr David Long (Doulos) Gold Sponsor

Track 3 – Verification FPGA 1

Speed up VHDL verification significantly by making a better testbench architecture and a simpler test sequencer

Espen Tallaksen (EmLogic)

12:30 Lunch and Networking
13:30 Speaker Name (Synopsys) Platinum Sponsor
14:00 Speaker Name (Jump Trading ) Gold Sponsor

RISC-V verification and implications of the 5:1 ratio of DV to design engineers

Simon Davidmann (Imperas Software)

14:40 Speaker Name (Company Name) Gold Sponsor
15:00 Refreshments and Networking
Multi-Track Session (PM)
Track 1 – Latest topics in Verification

Verification Makeover with RISC-V Processor Designs

Lavanya Jagan (Vyoma Systems Private Limited)


User experiences with open-source mainstream verification techniques

Srinivasan Venkataramanan,Deepa Palaniappan (AsFigo Technologies)

16:10 Session 2 – Speaker 3
Track 2 – Student Session 2

Is it easy to get started with UVM, or should I use Formal instead?

Dr David Long (Doulos) Gold Sponsor

Track 3 – Verification FPGA 2

Faster than “Lite” Verification Component Development with OSVVM

Jim Lewis (SynthWorks Design Inc)

Track 4 – UVM for AMS Verification

Renesas’s Submission to the UVM-(A)MS working group

Peter Grove,Steven Holloway (Renesas)

16:30 Event Closes


VF2023 was made possible through the generosity of the following sponsors. If you would like to become a VF2023 sponsor please Contact Us.