User experiences with open-source mainstream verification techniques

For well over a decade, ASIC and FPGA design verification has adopted modern techniques such as Object-Oriented Programming (OOP), assertions, Unit Testing, constraint random generation, coverage driven verification, Static checking and more. As with many such techniques, first few years are prototyped using proprietary technologies/tools and once found suitable, it goes through a standardization approach (through bodies such as Accellera, IEEE etc.). SystemVerilog (IEEE 1800) is one of the key languages used in Design Verification and UVM (IEEE 1800.2) is the most popular methodology around SystemVerilog.

Lack of open-source tools with good SystemVerilog support has been a let-down in this industry in the 2010’s. Given the vast adoption of these techniques, many efforts have gone in to address this by open-source enthusiasts across the globe. In this paper, we share our experiences with some of the latest open-source verification techniques available for wider ecosystem. We start with simple Linting techniques and show what is available as part of Verible, Icarus etc. Specifically, we will share few custom rules coded by our team on these open-source platforms. Then we show how SVUnit, an open-source Unit Testing framework works with Verilator. We highlight some of the recent fixes provided by our team to get SVUnit working with recent Verilator version.

Switching gears, we then show how a complete Checker IP (SVA based) for AMBA protocol is ported to work on Verilator with support for concurrent assertions (SVA). Given the SVA support is still maturing in Verilator, our team had to adapt the code to be restricted to what the tool supports. We also developed unit tests to verify these properties in Verilator. We will share our findings, potential areas to improve, etc. Our intention is to make this code base available as part of GO2UVM library. Finally, we will show the roadmap of running complete UVCs on Verilator (depending on the publicly available support for UVM in Verilator) with an APB UVC.

Srinivasan Venkataramanan : Srini is an influencer and a technology entrepreneur with extensive knowledge of Semiconductor chip design flow, languages, tools, and methodologies. As part of his latest venture, AsFigo Technologies, he is mainly focused on applying the latest technologies to address current bottlenecks in the chip design and verification process, with specific focus on open-source based deployments. Srini is also a globally reputed trainer in the field of ASIC & FPGA design verification and has trained more than 15,000 engineers on live classrooms. He also has solid EdTech presence via platforms such as Udemy with reach spanning to 110+ countries, 6000+ students and 8500+ hours of teaching.

Srini actively participates in evangelizing the latest languages, tools and methodologies in semiconductor design flow across the globe through various industry standardization committees, leading various GOTO conferences in the design verification field in multiple capacities. Srini is a published author with multiple books, articles, blogs etc. He is also a keen contributor to the open-source ecosystem and contribute to flows, tools, and libraries.

Deepa Palaniappan : Deepa Palaniappan is a seasoned engineer working on multiple disciplines in IC design and verification. Her interests include open-source simulators such as Verilator, Icarus and libraries/frameworks such as GO2UVM, SVUnit etc. She contributes to few open-source projects such as SVA IP on Verilator, MathLib development etc. She is consulting on FPGA design and verification to remote clients based in Europe.