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Speed up VHDL verification significantly by making a better testbench architecture and a simpler test sequencer

Conference: Verification Futures 2023 (click here to see full programme)
Speaker: Espen Tallaksen
Presentation Title:

Speed up VHDL verification significantly by making a better testbench architecture and a simpler test sequencer


Verifying complex DUTs can be time-consuming and difficult, - and verifying for instance a module or FPGA with multiple simultaneously active interfaces, even more so. Even a simple UART has error-prone corner cases that are very difficult to reach.

Unfortunately, most testbenches have an architecture that doesn’t allow a simple approach to this challenge, - *even* when the architecture is quite structured. The only good solution here is a testbench architecture that allows multiple interfaces to be simultaneously controlled and skewed, with simple, understandable commands from one single test sequencer.

The above challenge typically applies for control oriented DUTs, whereas the main challenge for more datapath oriented DUTs often is to assure that the right combinations of values have been tested. And for protocol oriented DUTs both challenges apply.

The open source UVVM (Universal VHDL Verification Methodology) has been developed to address exactly these challenges, and is in fact the only verification methodology that can do all of the above. During the last 6 years, the European Space Agency (ESA) has run two major projects helping extend UVVM even further, thus providing a great tool for their suppliers to improve quality and reduce development time. UVVM is the fastest growing verification methodology world wide.

With UVVM you can easily start transactions on multiple interfaces at the same time, or you can skew one interface with respect to another. You can also wait for one or more interfaces to go inactive, or even wait for a specific transaction to be finished. All managed via simple high-level commands from one single sequencer, as this allows the best control and overview possible.

UVVM released new functionality on Enhanced Randomisation and Functional Coverage in October 2021, and as always with UVVM, testbench readability, overview and user friendliness where it matters the most, were the highest priorities.

This presentation will show you why and how, - and you will even get a mini course on Functional Coverage and hopefully a better understanding of cycle related corner cases.

Speaker Bio: Espen Tallaksen is the CEO of EmLogic, in Norway.
Espen is also the author and architect of the Open Source UVVM (Universal VHDL verification Methodology), that is currently used by 40% of all FPGA designers in Europe.

He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given lots of presentations at various international conferences with great feedback. He is also giving courses on FPGA Design and Verification.

Key Points:
  • The best possible overview and readability significantly improve quality, efficiency and reuse
  • Randomisation and Functional coverage - brief introduction and usage, including explanation of optimised randomisation
  • High level (transaction level) commands allow even SW developers to read and write test cases, and you can control everything in your testbench from one single, sequential test process
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