|Conference:||Verification Futures 2023 (click here to see full programme)|
|Presentation Title:||RISC-V verification and implications of the 5:1 ratio of DV to design engineers|
It has been reported that a typical SoC project plan assumes 1 DV (Design Verification) engineer to every design engineer as a basic 1:1 ratio. But for processor verification, the ratio of DV engineers is closer to 5:1. The rapid growth in the adoption of RISC-V and the design freedoms offered by the open standard ISA (Instruction Set Architecture) specification is driving a new wave of processor developers pushing the boundaries of optimized processors. As the industry prepares for the coming tsunami of verification work this talk highlights the growing RISC-V Verification Ecosystem based on open standards and extensions to the classic SoC methods of SystemVerilog and UVM.
RISC-V represents the greatest shift in verification responsibility as the challenge of processor verification shifts to all developers exploring the new design freedoms of RISC-V
|Speaker Bio:||Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit, which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.|