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Renesas’s Submission to the UVM-(A)MS working group

Conference: Verification Futures 2023 (click here to see full programme)
Speaker: Peter Grove,Steven Holloway
Presentation Title: Renesas’s Submission to the UVM-(A)MS working group

Explanation on how UVM can be applied to DMS/AMS using a concept of a MS Bridge module. The focus will be on an AMS Device-Under-Test, but the concepts work for DMS. The audience will be guided over subtleties of AMS simulators and a known limitation with the proposal and possible solutions. There will be a walk though of how this was applied to a Mixed signal block. The audience should not take way the current implementation until an official release of UVM-AMS has been made. The current contents of the presentation and example code has been shared to the EDA community to feed into a white paper on the topic. Steven will cover the UVM aspects and Peter will go over mixed signal parts.

DMS – Digital-Mixed-Signal also referred to as Real-Number-Modelling

AMS – Analog-Mixed-Signal

MS – Mixed Signal

Speaker Bio:

Peter Grove:Peter has worked in the industry starting back in 2001 when he joined a small company called Wolfson MicroElectronics, where he was project lead for more than 15 production devices. Since then Peter has only worked at one other company, Nujira, before joining Dialog (now Renesas) at their Edinburgh office. Peter has been with Dialog since 2014. Peter’s background has been main digital design, but has over the years taken charge of many large mixed signal devices that are in volume production and been exposed to enough analogue design work to appreciate the issues they face in verification. Peter has an eye for looking for ways in which techniques can be done to improve chip level coverage, simulation runtime improvement to name a few. Peter is also in a unique position that during his days at Wolfson he was a key player in defining their schematic/Layout tool set with integrated revision control. This has allowed Peter to gather a large number of skills not just in design work but in all the backend flows and EDA tools, understanding different netlist types and how the tools work.

Peter’s technical interests are mixed signal and analogue verification methodologies, design flows. Peter also is an Acellera SystemVerilog-AMS committee chair, UVM-AMS member/key contributor making sure the ‘users’ feedback on the language is considered and not what the vendors just want to support.

Steven Holloway:Steve has 20+ years’ experience of digital verification including eRM, OVM, UVM and formal property checking. He has led the verification of large-scale consumer SoC projects. He joined Dialog Semiconductor in 2011 and previously worked for Doulos, NXP and Trident Microsystems. He joined the Technical Ladder in 2015.

Steve has presented at multiple external conferences including a panel session at DVCon US. He participates in industry standards bodies and has contributed code to the Accellera UVM-AMS working group

Key Points:
  • Simulator initialization and synchronisation between engines.
  • How to go from classical UVM to UVM-(A)MS.
  • Key differences in stimulus generation and monitoring.
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