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Introduction to Verification and SystemVerilog for Beginners

Conference: Verification Futures 2023 (click here to see full programme)
Speaker: Dr David Long
Presentation Title: Introduction to Verification and SystemVerilog for Beginners
Abstract: It is essential to verify the correct operation of a digital FPGA, ASIC or SoC design before it is manufactured. However, making sense of the verification methodologies, languages and tools used, can be challenging, when first encountered. This presentation gives a brief overview of the current verification landscape, including verification objectives, simulation and formal verification approaches, the languages used and the tools required. It then introduces the main features of SystemVerilog – the most popular language used for verification today. This overview will provide a foundation for verification novices, who subsequently wish to study UVM or Formal Verification in greater detail.
Speaker Bio:

Dr David Long has been a key member of the Doulos technical team since 2001, specialising in Hardware Description Language-based design and verification. As well as developing, writing, and presenting training courses in leading-edge methodologies for embedded SW development, FPGA, ASIC and SoC design and verification, David regularly contributes to technical papers, tutorials, and conference presentations at major industry events world-wide. He has also provided project support and consultancy for industrial clients in the fields of digital/mixed-signal IC design and verification.

Courses taught include: SystemVerilog, SystemC, UVM, VHDL, Verilog, VHDL-AMS, C and C++ Programming for Embedded Systems and Embedded System Security. David was co-author of the IEEE Standard 1666-2005 SystemC Language Reference Manual and wrote the draft LRM for the SystemC Control, Configuration and Inspection (CCI) working group.
He has a PhD in Simulation of Mixed-Signal Circuits and a MSc in VLSI Design.
Before joining Doulos, David worked for 10 years at a UK university where he was a Senior Lecturer in Microelectronics. In total, he has over 35 years’ experience of electronics design and verification in both industry and academia.

Key Points:
  • Approaches to Verification.
  • Creating a testbench with SystemVerilog classes.
  • Use of constrained-random stimulus and functional coverage in SystemVerilog.
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