|Conference:||Verification Futures 2023 (click here to see full programme)|
|Presentation Title:||How to build the future verification engineers ?|
The last 20 years, we kept claiming that about 50% of the overall digital development is spent in verification. Companies therefore need these people to be trained to the most advanced verification techniques and methodologies in order to get the best ROI from this workload.
If universities have open dedicated verification courses, it seems though this does not definitely represent 50% of the lectures. And when we ask what engineering students want to do in their lives, only a few say spontaneously "I want to be a Verification Engineer".
In the meantime, corporations, startups and SMBs had to grow their teams in verification. Recruiting a verification engineer became a real challenge and we all had to turn to training design engineers or software engineers to verification either through external trainings or even through inhouse self-made trainings.
As the languages and libraries we are using are complex, ramping up an engineer to verification techniques takes some time. Surely, knowing these techniques is a start to become a good verification engineer, but we still have to learn about the Methodology with a big M (not the one in UVm) and about the Verification Mindset. Furthermore, with the arrival of more and more powerful AI, we can reasonably ask ourselves if the verification job is not going to change in the coming years.The challenge of building the future verification engineers can therefore be seen from different angles.
François Cerisier has over 20 years of verification experience and is recognized as an expert in the field. He started as a Verification Engineer working for Infineon and Broadcom at the early age of Specman and then moved to consulting to provide his own expertise in the field of verification. After a career as a verification consultant for startups as well as blue chip companies, he has founded AEDVICES to provide design and verification services and as well as turn key solutions. He developed trainings in the area of SystemVerilog, UVM as well as on the overall verification methodology.