|Conference:||Verification Futures 2023 (click here to see full programme)|
|Presentation Title:||Faster than “Lite” Verification Component Development with OSVVM|
Verification components are a fundamental part of an advanced testbench framework. OSVVM creates verification components with three steps: create the transaction interface, create the transaction API, and create the verification component (VC) functionality.
OSVVM has codified (internally standardized) the transaction interface and the transaction API for address bus interfaces (such as AXI, APB, Avalon, …) as well as for stream interfaces (such as UART, AxiStream, …). We call these our Address Bus and Stream Model Independent Transactions and provide these as part of our “osvvm_common” VC support library.
The benefit to VC developers creating an OSVVM address bus or streaming VC is that there is only one step to create a VC – create the VC functionality. For a basic implementation of the VC, this step is no more complex than creating the functionality in a VHDL procedure.
The benefit to test developers is that verification components of the same class (address bus or stream) either implement all or a subset of the OSVVM Model Independent Transactions – hence, test developers already know the API (call interface) to write tests. This makes writing tests easier. It also facilitates the re-use of test sequences between interfaces of the same class.
This presentation is a guided walk through of writing an OSVVM VC using the Model Independent Transactions.
At the end of the day, OSVVM does not need a "Lite" version of our verification framework because we make writing verification components as simple as writing a procedure. Furthermore, any of OSVVM's growing library of verification components can be used as a template for getting started.
Before attending this session, you may find it helpful to see our recorded DVClub presentation,Open Source VHDL Verification Methodology (OSVVM), Leading Edge Verification for the VHDL Community- PDF & Video
Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.