|Verification Futures 2019 (click here to see full programme)
|Steve Holloway, Dialog Semiconductor
|Making Formal Normal: Integrating FV into your Verification Methodology
|Constrained-random simulation has long been established as the mainstay of functional verification. Well-defined methodologies exist to help the engineer create efficient and reusable verification components. On the other hand, formal verification offers potentially exhaustive verification using a fundamentally different approach. The underlying language (SVA) is the same for both formal and simulation. This presentation describes some tips and tricks to help combine the use of formal and simulation-based approaches to achieve metrics closure for a design.
|Steve has 19 years experience of functional verification methodologies including eRM, OVM, UVM and formal property checking. He has led the verification of large scale consumer SoC projects. He joined Dialog Semiconductor in 2011 and previously worked for Doulos, NXP and Trident Microsystems.
Steve would like to thank Wolfgang Mayerweiser for his invaluable input into the presentation.