|DVCLUB Europe | Overview of the Open Source VHDL Verification Methodology (OSVVM)
|Jim Lewis, VHDL Evangelist, SynthWorks Design Inc.
|OSVVM is an advanced verification methodology that defines a verification framework, VHDL utility library, VHDL verification component library, and a scripting library. OSVVM simplifies your FPGA and ASIC verification project from start to finish. It is easy enough to use on small blocks and powerful enough to use on large, complex chips or systems.
OSVVM supports the same capabilities that verification languages such as SystemVerilog + UVM support – including transaction level modelling, verification components, functional coverage, constrained random tests, Intelligent Coverage random tests, data structures (such as scoreboards, FIFOs, and Memories), error logging and reporting (counts tracked internally), message filtering, and advanced reporting (HTML and JUnit XML for CI/CD).The intention of OSVVM goes beyond capability though – OSVVM intends to make verification easy, readable, and fun.Key Points:
|Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
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