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Overview of the Open Source VHDL Verification Methodology (OSVVM)

DVClub Europe Meeting – April 2022

Event at a Glance

Tuesday 26th April, 2022

13:00 – 14:00 BST

FREE to attend Online

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Overview of the Open Source VHDL Verification Methodology (OSVVM)

A dedicated 1 hour additional DVClub with a talk from Jim Lewis, the founder of SynthWorks. Jim is an innovator and leader in the VHDL community. He has thirty plus years of design, teaching, and problem solving experience, and drives the Open Source VHDL Verification Methodology (OSVVM) development
OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC.

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Agenda (BST):

Time Session Description           Slides              Videos
13.00 BST
17:30 IST
OSVVM: Leading Edge Verification for the VHDL Community
Jim Lewis, VHDL Training Expert, SynthWorks
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About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.


DVCLUB Europe is made possible through the generosity of our sponsors.

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