|Conference:||DVCLUB Europe | Formal Verification Adoption Made Easy|
|Speaker:||Neil Johnson, Senior Product Engineering Manager, Siemens EDA|
|Abstract:||Formal is scary… or at least that’s what I always thought. This talk documents an unlikely journey into formal for a verification engineer who’s spent an entire career using simulation. You’ll see the progression from user-friendly formal apps to first steps of formal property checking; the practical idea of exhaustive module level formal verification to the promise of property-driven development. Verification engineers will take ideas for using formal and simulation as complementary technologies. Design engineers will see formal property checking as an effective technique for early detection and elimination of RTL bugs. Turns out formal isn’t scary at all.
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|Speaker Biography:||Neil Johnson is a long time verification engineer with a history in product development as both a full-timer and a consultant. He now works with Siemens as a Senior Product Engineering Manager responsible for Questasim.
Nick has worked for Cadence since 2007 in a variety of RnD roles across verification. He currently works in the Systems and Verification Group and is responsible for SoC Verification and is the Architect of System VIP.
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