Event at a Glance
Tuesday 7th September, 2021
12:00 – 13:30 BST
FREE to attend Online
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Formal Verification Adoption Made Easy
Four verification experts will spend 20 minutes each outlining tools and methodologies aimed at making Formal Verification Adoption Made Easy.
13.20 BST 17:50 ISTClosing Remarks
|12.00 BST 16:30 IST||Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
|12.05 BST 16:35 IST||I’m Excited About Formal…My Journey From Skeptic To Believer
Neil Johnson, Senior Product Engineering Manager, Siemens EDA
|12.30 BST 17:00 IST||Formal Verification Adoption Made Easy
Alexandre Esselin Botelho, Sr. Principal Application Engineer, Cadence Design System
|12.55 BST 17:25 IST||Formal for Easing the SystemC/C++ Verification Burden
Vlada Kalinic, Product Specialist (for SystemC), OneSpin A Siemens Business
|13.30 BST 18:00 IST||Close|
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
DVCLUB Europe is made possible through the generosity of our sponsors.