|Conference:||DVCLUB Europe | Formal Verification|
|Speaker:||Jeremy Levitt, Principal Engineer, Questa Formal R&D, Mentor, A Siemens Business|
This time yesterday you kicked off a formal analysis – and it’s still running! Is it making any progress, or should you kill it now and start over? In this talk we will show how to make an informed decision using “engine health” monitoring, a snapshot of the active logic being used by the analysis, and making an honest appraisal of the assumptions you applied at the beginning of the run. Plus: we’ll show how a secure mobile app can be employed to keep track of progress of formal runs when you are away from your workstation.
|Speaker Biography:||Dr. Levitt is a Principal Engineer in the Formal Verification Group of Mentor, A Siemens Business. He oversees R&D with a focus on algorithm development. Jeremy earned his Ph.D in Electrical Engineering from Stanford in 1997, M.S. in 1993 and a B.A.Sc in Engineering Science from the University of Toronto in 1991.|
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