DRDO Event

Agenda for Internal Session

Workshop Runsheet

Session Agenda

Morning Sessions

Time	Topic	Presenter	Key Focus
10:15 – 10:25 AM	Welcome & Workshop Overview	Bharath/Ganesan	Introduction to airborne embedded systems, workshop objectives, development lifecycle overview
10:25 – 10:45 AM	Concept to Product Development Journey	Bharath/ Ganesan	System architecture, development phases, technology selection, airborne design challenges, certification awareness
10:45 – 11:05 AM	Specifications to Design & Validation	Srinidhi	Requirement capture, system specifications, design decomposition, traceability, verification and validation planning
11:05 – 11:10 AM	Transition & Q&A — Interactive discussion
11:10 – 11:30 AM	FPGA-Based Embedded Systems for Airborne Applications	Raju Bhandarai/ Sadanand	FPGA fundamentals, architecture selection, airborne use cases, design flow overview
11:30 – 11:50 PM	FPGA Design Implementation & Integration	Raju Bhandarai/ Sadanand	RTL development, IP integration, simulation, timing closure, hardware bring-up considerations
11:50 – 11:55 PM	Transition & Q&A — Interactive discussion
11:55 – 12:15 PM	PCB Design, Layout & System Packaging	Nataraju	Schematic-to-layout flow, multilayer boards, packaging technologies, SIP (System-in-Package) concepts, designfor-manufacturing considerations
12:15 – 12:35 PM	Signal Integrity & Power Integrity in High-Speed Systems	Rajesh B J	SI/PI fundamentals, routing challenges, stack-up planning, EMI/EMC awareness
12:35 – 12:55 PM	Mechanical Design & Thermal Analysis	Vinod Kumar	Enclosure design, airborne environmental requirements, thermal management, vibration considerations

Afternoon

Time	Topic	Presenter	Key Focus
12:55 – 1:15 PM	System Validation, Manufacturing Readiness & Closing Discussion	Panel (All Speakers)	Prototype realization, qualification strategy, manufacturing readiness, participant Q&A
1:15 – 2:00 PM	Lunch & Networking

Rotation Schedule

Slot 1 2:00 PM – 2:30 PM

Batch	Location	Tour Lead	Coverage
Batch A	Reliability Lab	Reliability Team	Environmental testing, vibration, thermal cycling, qualification methodology
Batch B	ATE Lab	ATE Team	Automated test systems, production test flow, board-level validation
Batch C	Engineering Interaction Zone / Demo Area	FPGA & PCB Team	FPGA development boards, PCB samples, packaging examples, design review artifacts

Slot 2 2:30 PM – 3:00 PM

Batch	Location	Tour Lead	Coverage
Batch A	ATE Lab	ATE Team	Automated testing and production validation
Batch B	Engineering Interaction Zone / Demo Area	FPGA & PCB Team	FPGA demonstrations, PCB realization examples
Batch C	Reliability Lab	Reliability Team	Qualification and reliability testing

Slot 3 3:00 PM – 3:30 PM

3:15 – 3:25 PM	Reconvene at Main Hall
3:25 – 3:30 PM	Workshop Wrap-up, Feedback Collection & Group Photograph

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

DRDO Event

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ML Verification Turns Convention on its Head

An Emulation Strategy for Artificial Intelligence Designs

AI chips must get the math right

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