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Detection of Glitch-Prone Clock and Reset Propagation with Automated Formal Analysis

Conference: DVCLUB Europe | Selection of 2021 DVCon/DAC Verification Papers
Speaker: Sulabh-Kumar Khare: Staff Engineer and Kaushal Shah: Senior Member Technical Staff, Siemens EDA.

Modern SoCs employ various complex reset and clock architectures to handle ever increasing demand for timing and power efficiency. Advanced clock and reset architectures can lead to complex circuitry on the clock and reset paths. The logic on the clock and reset paths is prone to propagation of glitches. The session will present a unique method based on identification of unique combinational expressions on the clock and reset path and use automatic formal analysis to zero-in on real clock and reset glitch paths that can make your chip unpredictable if not addressed early. Appropriate debug aids based on combinational expression analysis of the clock or asynchronous reset path logic will be presented to quickly zoom to the logic that’s responsible for introducing the glitch.

3 Key Points:

  • Advanced architectures can be prone to glitches in clock and reset paths
  • Formal analysis may be used to identify clock and reset path issues early in the development cycle
  • Additional debug technologies for clock or asynchronous reset path logic can assist in the process
Speaker Biography: Sulabh-Kumar Khare:
Sulabh oversees the development of the Questa CDC product line at Siemens EDA. He has over 14 years of experience in developing EDA software for the design and verification domain. He holds a Masters degree in VLSI design from IIT Kharagpur.Kaushal Shah:
Kaushal is a senior member of R&D with Questa Static and Functional Verification team. He post-graduated in Microelectronics and VLSI design from IIT Kharagpur.


DVCLUB Europe is made possible through the generosity of our sponsors.

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