Event at a Glance
Tuesday 8th February, 2022
12:00 – 13:30 BST
FREE to attend Online
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Selection of 2021 DVCon/DAC Verification Papers
Five verification experts will spend 15/20 minutes presenting versions of 2021 DAC/DVCon papers.
|12.00 BST 17:30 IST||Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
|12.05 BST 17:35 IST||Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage
Tim Blackmore, Senior Principal Verification Engineer, Infineon Technologies
|12.25 BST 17:55 IST||Detection of Glitch-Prone Clock and Reset Propagation with Automated Formal Analysis
Sulabh-Kumar Khare: Staff Engineer and Kaushal Shah: Senior Member Technical Staff, Siemens EDA
|12.40 BST 18:10 IST||DVCon Panel Summary: SoC Verification Challenges
Nick Heaton, Distinguished Engineer, Cadence Design Systems
|12.55 BST 18:25 IST||Formal Verification of Safety Mechanisms
Keerthi Devarajegowda, Staff Engineer, Infineon Technologies AG
|13.10 BST 18:40 IST||SoC Verification and the Synthesizable VerificationOS
David Kelf, CEO, Breker Verification Systems
|13.25 BST 18:55 IST||Closing Remarks|
|13.30 BST 19:00 IST||Close|
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
DVCLUB Europe is made possible through the generosity of our sponsors.