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Selection of 2021 DVCon/DAC Verification Papers

DVClub Europe Meeting – February 2022

Event at a Glance

Tuesday 8th February, 2022

12:00 – 13:30 BST

FREE to attend Online

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Selection of 2021 DVCon/DAC Verification Papers

Five verification experts will spend 15/20 minutes presenting versions of 2021 DAC/DVCon papers.

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Agenda (BST):

Time Session Description           Slides              Videos
12.00 BST Welcome and Introduction

Mike Bartley, Senior Vice President – VLSI Design, Tessolve

12.05 BST Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage

Tim Blackmore, Senior Principal Verification Engineer, Infineon Technologies

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12.25 BST Detection of Glitch-Prone Clock and Reset Propagation with Automated Formal Analysis

Sulabh-Kumar Khare: Staff Engineer and Kaushal Shah: Senior Member Technical Staff, Siemens EDA

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12.40 BST DVCon Panel Summary: SoC Verification Challenges

Nick Heaton, Distinguished Engineer, Cadence Design Systems

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12.55 BST Formal Verification of Safety Mechanisms

Keerthi Devarajegowda, Staff Engineer, Infineon Technologies AG

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13.10 BST SoC Verification and the Synthesizable VerificationOS

David Kelf, CEO, Breker Verification Systems

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13.25 BST Closing Remarks
13.30 BST Close

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.


DVCLUB Europe is made possible through the generosity of our sponsors.

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