|Conference:||DVCLUB Europe | Selection of 2021 DVCon/DAC Verification Papers|
|Speaker:||Tim Blackmore, Senior Principal Verification Engineer, Infineon Technologies.|
|Abstract:||The presentation describes how test selection using machine learned novelty can be used to significantly reduce the number of simulations needed to close coverage, including on real-world coverage models for complex IPs. The results of a large-scale experiment are given suggesting the time spent to close coverage can be reduced from 6 months to around 3 months for a highly configurable RADAR data processing unit.
3 Key Points:
|Speaker Biography:||Tim is a Senior Principal Verification Engineer at Infineon Technologies, based in Bristol. His research focus is improving the efficiency of the verification of complex IPs, subsystems and SoCs. He is also the Global Verification Manager for Infineon’s current family of Aurix3G microcontrollers and is a Visiting Industrial fellow at the University of Bristol.|
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