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Assertion IP for Cache Coherency Verification

Conference: DVCLUB Europe | Cache Coherency Verification
Speaker: Alex Netterville, Synopsys
Speaker Title: Assertion IP for Cache Coherency Verification

This presentation will discuss the concept of cache coherency, and will look at the approach to the problem of its verification. It will finally delve into the Synopsys Assertion IP product offerings that can help address this complex verification need.

Key Points:

  • Cache coherency verification is critical for high-speed multiprocessor system.
  • Formal exhaustive analysis is best for cache coherency verification.
  • Synopsys VC Formal and its AIPs can address this complex verification need.
Speaker Biography:

Alex is an Applications Engineer working within the VC Formal team at Synopsys. He has responsibility for various Assertion IP products at Synopsys, and has also undertaken consulting projects with large customers. Previously, Alex worked at Imagination Technologies in the Power VR Group doing formal verification. Before that, he worked with Axiomise on their RISC-V verification IP. Prior to this, Alex worked in the CPU group at ARM in a variety of design and verification capacities. Alex lives in Derbyshire with his wife and 4 kids, and their cat Theo.


DVCLUB Europe is made possible through the generosity of our sponsors.

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