About the Speaker

Levon Khachatryan is the founder and director of VoskenAI Ltd, a UK-based company developing a platform that transforms natural-language specifications into silicon-ready, verified SystemVerilog RTL. His background combines hardware engineering with academic training in applied data science and physics. His current work explores how modern LLMs can be integrated into production-grade silicon design and verification flows.

Free-Form Drift and Its Cure: Architectural Pre-Commitment for LLM-Generated RTL

Overview

Ask an LLM to write SystemVerilog from a natural-language specification and it will oblige, producing code that is often wrong in ways invisible until simulation. Free-form generation gives the LLM too much freedom to silently drift from the intended hardware architecture. VoskenAI’s production pipeline solves this through Architectural Pre-Commitment: fixing the microarchitecture before the LLM writes a single line of RTL. The model’s task becomes filling strictly defined slots within a fixed structure. We share
production results, boundary cases, and what this implies for LLM intelligence in hardware design.

Key Points

• Free-form generation gives LLMs too much freedom to silently drift from the intended hardware architecture, producing code that is plausible, confident, and wrong in ways invisible until simulation.
• Architectural Pre-Commitment fixes the microarchitecture before any RTL is written, collapsing the LLM’s task to filling strictly defined slots within a fixed structure.
• Production results from a multi-stage pipeline raise a question for the industry: if LLMs need this level of scaffolding to produce reliable RTL, how much of their design intelligence are we actually leveraging?