Design and Verification of an AI Accelerator in Neuromorphic Chips

Neuromorphic computing promises energy-efficient intelligence by emulating brain-inspired architectures. This presentation describes the design and verification of an AI accelerator integrated within neuromorphic chips. The architectural choices for spiking neural network acceleration, including event-driven computation, parallel synaptic processing, and on-chip learning support. The design flow covers hardware–software co-design, precision trade-offs, and memory optimization for low-power operation based on approximate computing. Simulation and verification of various approximate multipliers and adders are carried in EDA Playground by DOULOS and implemented on ZedBoard FPGA hardware. The results demonstrate scalability, robustness, and significant gains in latency and energy efficiency for edge AI applications in autonomous sensing and control systems.

Mrs. Abhyarthana Bisoyi is an Assistant Professor in the School of Electronic Sciences at Odisha University of Technology and Research (OUTR). She has completed her Bachelors in Electronics and Communication Engineering in the year 2011 and Masters from National Institute of Technology Rourkela (NIT Rourkela) in Electronics and Instrumentation Engineering in the year 2013. From then to now, she has teaching experience of more than 12 years. She has guided 22 Masters students and more than 100 undergraduate students. She is current pursuing her PhD from OUTR and her research area includes Digital VLSI, Approximate and Neuromorphic Computing.