EEnet verification of a Multilevel DCDC converter IC

Error: Contact form not found.

Get In Touch

Error: Contact form not found.

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

AI chips must get the math right

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification

3 Key Points:

Floating-point unit (FPU) for AI chips

FPU Formal Verification App

Compliance with IEEE-754

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

Please fill the form below

Error: Contact form not found.

Please fill the form below

SUBMIT RESUME

Error: Contact form not found.

SUBMIT YOUR RESUME

Conference:	Verification Futures 2025 (click here to see full programme)
Speaker:	Paul Denny
Presentation Title:	EEnet verification of a Multilevel DCDC converter IC
Abstract:	Multilevel DCDC converters offer many advantages for compact high efficiency power conversion in mobile devices. These include small form-factor, low ripple and high efficiency. However, the multiple powertrain switch states must be algorithm controlled in real time to maintain correct fly capacitor charge status and stable, efficient operation. In addition, the IC is measuring and reporting multiple telemetry parameters through a delta sigma ADC with the modulator and decimation filters split across analog and digital domains, respectively. Verifying this complex mixed signal IC requires the simultaneous simulation of pure digital RTL, signal-flow analogue behavioural and, crucially, conservative KCL network equations in the output switch, inductor, capacitor resistor network. This presents a significant challenge to most established mixed signal simulation tools. AMS based approaches are far too slow and digital-on-top wreal models are unable to deal with the conservative equations necessary to model the DCDC converter output behaviour. Cadence EEnets leverage SystemVerilog user defined nets (UDNs) and user defined resolution functions (UDRs) to model critical conservative networks with similar levels of accuracy to SPICE like simulators, but with the dramatically faster simulation times obtainable from event driven simulation. This presentation describes the application of Cadence EEnets to this verification challenge, the difficulties encountered and the effectiveness of the final model in terms for speed and accuracy
Speaker Bio:	Paul Denny has over 40 years’ experience in the IC industry managing mixed signal design teams on products ranging from CMOS Fractional N RF frequency synthesizers, 10Gbps DFE equalizers and advanced power management ICs. He has a special interest in mixed signal SOC verification methodologies.
Key Points:	EEnets can provide SPICE like accuracy for critical system nets EEnets can be over 1000x faster than other AMS methodologies EEnets require specialist expertise covering Analog Schematic, Digital HDL and Simulation (convergence, timestep control, accuracy limits etc)

EEnet verification of a Multilevel DCDC converter IC

About Tessolve

Solutions

Tessolve Labs

Insights

Connect with us

ML Verification Turns Convention on its Head

An Emulation Strategy for Artificial Intelligence Designs

AI chips must get the math right

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below