Mixed-signal verification faces an inherent trade-off between simulation accuracy, development effort, and execution speed. This paper presents a systematic methodology for selecting optimal abstraction levels in SystemVerilog modeling, demonstrated through practical case studies. The first example transitions from a SPICE-level operational amplifier to a structural SystemVerilog model using voltage-current-resistance (VIR) nettypes. We demonstrate how controlled sources and basic passive components can preserve essential analog characteristics while achieving a significant TAT speedup. We present how different abstraction choices impact:

• Model development time
• Verification coverage
• Simulation performance
• Accuracy of key parameters

Our methodology provides concrete guidelines for selecting abstraction levels based on verification requirements, available resources, and performance targets.

Evgeny graduated from the Micro- and Nano-Electronics Institute at the Moscow Engineering Physics University. He spent eight years in the aviation industry as an analog design engineer and multi-chip module engineer before transitioning to the EDA industry. For the past six years, he has specialized in AMS verification and Functional Safety products, serving as both an FAE and a PE.