The Era of Agentic Engineering – Roadmap to Level 5

We are now in the era of pervasive intelligence from voice assistants, advanced robotics, drone-based delivery to autonomous cars, and chatbots. This begs the question, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. With the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification? In this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today.

Priya Chevuturi is a Staff Application engineer for Verification Software at Synopsys based in Reading, UK. She has over 12 years of experience in the semiconductor industry. Post her master’s degree graduation in Microelectronics from Hamburg University of Technology, Germany, she has worked extensively as an FPGA engineer developing products for various applications including automotive, railways, industrial and computer vision technologies. As a Verification AE she supports customers in the UK on the simulation, debugging and planning tools in Synopsys Verification Continuum. She enjoys reading non-fictional books during her spare time.