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The Era of Agentic Engineering – Roadmap to Level 5

Conference: Verification Futures 2025 (click here to see full programme)
Speaker: Bradley Geden
Presentation Title: The Era of Agentic Engineering – Roadmap to Level 5
Abstract:

We are now in the era of pervasive intelligence from voice assistants, advanced robotics, drone-based delivery to autonomous cars, and chatbots. This begs the question, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. With the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification? In this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today.

Speaker Bio:

Bradley Geden is the Senior Director of Product Management for Verification Software at Synopsys based in Sunnyvale, CA. He has over 20 years of experience in the EDA industry covering a broad range of domains from Custom Design, Circuit Simulation, Digital Implementation and Verification in both Product Management and Sales Roles at Synopsys and Siemens EDA. Prior to entering the world of EDA he was an Analog Mixed-Signal Design Engineer working on Energy Measurement and Wireless Communication Chips. In his spare time, Bradley enjoys travelling and exploring the world with his wife, preferably on a sail boat!

Key Points:
  • We are now in the era of pervasive intelligence
  • Design Verification accounts for half the cost of designing a chip and the predominant cause of respins is functional issues.
  • Generative AI presents a once in a generation opportunity to revolutionize chip design and verification, delivering the next level of automation
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