Verification Futures » VF2025 UK » AVL – Bringing Industry Best Practise Testbench Design to Open Source

AVL – Bringing Industry Best Practise Testbench Design to Open Source

Conference:	Verification Futures 2025 (click here to see full programme)
Speaker:	Andy Bond
Presentation Title:	AVL – Bringing Industry Best Practise Testbench Design to Open Source
Abstract:	We’ve seen several presentations over the last few years around the productivity benefits of using the more feature rich (and zero compile time) Python language for verification. CocoTB enables this, by bringing simple, seamless simulator integration, but lacks the re-use methodology best practises of UVM, expected for commercial projects. AVL aims to bring the best of both worlds. A simple, programmer focused library to enable efficient test-bench development that can scale for the larger designs and teams required for modern verification. AVL, provided as open source, doesn’t attempt to replicate UVM or SystemVerilog. It cherry picks the best features and aims to implement them in the most familiar and user-friendly way, while taking advantage of the natural coding style of Python. Hopefully fixing some of the oversights we have all got used to working around on the way. In this presentation you’ll get a whistle-stop tour of the library’s key features: HDL style sized and signed variables (including half, single and double precision floating point numbers) Human and machine-readable log generation Native factory class with intuitive syntax User configurable test phases A simplified, industry expected TLM, agent, sequencer and driver re-use methodology Safe and reliable scoreboards Full constraint driven randomization for all data types Fully flexible functional coverage
Speaker Bio:	Andy has 25 years’ experience as a verification engineer and leader. After starting his career verifying processors for ST he was part of the foundation team for Icera before leading their verification team after the acquisition by NVIDIA. Having since built and developed teams for Cirrus Logic and in fintech, he is currently director of verification for Axelera AI, helping solve the verification challenges of the next generation of AI chips. AVL is the first in what he hopes to be a series of open-source resources aimed at simplifying design and verification for student, hobbyist and professional engineers.
Key Points:	Python has been growing in popularity as a verification language, but the lack of methodology has made adoption challenging UVM and SystemVerilog haven’t been evolving and can be frustratingly slow to develop AVL aims to provide the middle ground, enabling more efficient test-bench design

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

AVL – Bringing Industry Best Practise Testbench Design to Open Source

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