RISC-V Processor Verification Requires the Complete Toolbox

Today’s complex processor-based systems enable technological advances in many market segments, such as AI, high performance computing, and automotive. However, verification of these systems introduces new challenges, spanning architectural verification of a custom RISC-V processor to memory coherency in a system containing thousands of cores. As the complexity of the design increases, so does the need for new tools and methods beyond simulation and UVM testbenches. In this presentation, we will focus on RISC-V processors and present next-generation verification techniques that span the verification journey from a single RISC-V processor to complex systems with many RISC-V cores. To accommodate the flexible and evolving nature of the RISC-V ISA, as well as privilege mode features, out-of-order pipelines, interrupts and debug mode, RISC-V processor verification requires innovation in stimulus generation, comparison, and checking. The presentation will cover dynamic and formal approaches to verifying RISC-V cores, with topics including, but not limited to: ISA compliance verification and functional coverage, data path validation, functional verification of critical blocks, and security verification. Multi-core designs introduce a new set of challenges, such as ensuring fair access to shared resources and cache and memory coherence. This presentation will discuss solutions designed to address these issues and prevent costly bug escapes to silicon. The size of multi-core designs and multi-processor SoCs means that a simulation-only verification strategy is impractical. Hardware-assisted verification becomes essential to ensuring correct operation in the multi-core and multi-processor designs of today and the future. This presentation will demonstrate how next-generation processor verification tools and techniques combine with HAV platforms to create powerful and effective solutions. This presentation will elaborate the different decisions that go into the verification plan for RISC-V processors and processing subsystems and will discuss the different technologies and methodologies that are employed in a comprehensive approach to processor verification.

Simon is currently VP Engineering, Processor Modeling & Verification in Synopsys. Simon was founder and CEO of Imperas Software Ltd. until its acquisition by Synopsys in Dec 2023, and before that was founder and CEO of Co-Design Automation that created SystemVerilog from Verilog. In his career, Simon has been involved with 6 successful EDA startups as founder or first European employee which have been acquired for over $1billion in 2025 money. Simon has a BSc and MSc in EE from Essex Univ. UK, and was a visiting Professor at Queen Mary, University of London for over 10 years. He has given many conference keynote presentations, and numerous papers over the years, and has been awarded 5 patents.