Applying Generative AI in Post-Silicon Validation: Real Use Cases and Technical Insights

Post-silicon validation is one of the most demanding phases in the silicon lifecycle, where real hardware is stressed to uncover bugs that escaped pre-silicon verification. Despite extensive simulation, emulation, and formal verification, subtle issues especially those involving cache coherency, memory ordering, or multi-core synchronization often manifest only on silicon. Traditional approaches rely on constrained-random instruction generators, directed assembly tests, and workload-based stress tools, but these methods have limitations in scalability and in covering rare interleaving’s. Generative AI (GenAI), powered by large language models and domain-tuned generative frameworks, introduces a new paradigm. In post-silicon, GenAI can be used to automatically synthesize coherency stimulus programs, generate assembly/microcode sequences for stressing MESI/MOESI state transitions, or mutate existing directed tests to explore unanticipated access patterns. For example, a GenAI model can take a high-level directive such as “generate a four-core workload with simultaneous atomic operations to shared cache lines” and produce runnable test code that stresses invalidation, downgrade, and writeback races across cores.

Beyond stimulus generation, GenAI can assist in failure triage by summarizing long counterexample traces, correlating performance counter anomalies with expected states, and suggesting candidate root causes. These capabilities reduce debug turnaround time and allow engineers to focus on hypothesis validation rather than manual log sifting. Early experiments show that AI-generated stimulus can complement traditional random generators by increasing test diversity and reaching otherwise difficult-to-hit corner cases. This session will present real examples of GenAI applied in post-silicon validation of complex SoCs, highlighting both the measurable benefits (coverage, debug efficiency, reduced engineering effort) and the guardrails required to ensure correctness. Attendees will gain a deeper understanding of how GenAI augments, rather than replaces, existing validation flows, and how it can be systematically integrated into mission-critical post-silicon environments.

I am an experienced engineer with 7 years in SoC design and verification, currently focused on full-chip coherency verification of advanced, high-performance computing systems. At NVIDIA, I actively contribute to the validation of flagship architectures such as Grace Hopper and Blackwell GPUs, which power DGX-class platforms used across AI, data center, automotive, and HPC applications. I have a strong track record of verifying silicon tailored for AI acceleration, working closely with industry-leading designs that push the boundaries of compute, memory, and interconnect complexity. I hold a Master’s degree in Computer Engineering from the University of Southern California. Prior to NVIDIA, I developed firmware with a focus on security for Robert Bosch, gaining hands-on experience bridging low-level software and hardware security. Well-versed in modern computer architecture, I possess deep expertise in cache coherence protocols, multi-agent interconnect systems, and memory consistency models. My work centers on verifying complex heterogeneous SoC architectures, including CPU-GPU interactions under parallel, high-throughput workloads. I am passionate about enabling robust, scalable, and high-efficiency hardware that powers next-generation AI training and inference systems, continuously driven by the challenge of verifying correctness and security in large, tightly integrated computing platforms.