Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

Simulation performance has long been seen as the bottleneck to design verification. Performance in the thousands of instructions per second, even tens of thousands of instructions per second, makes running long tests on complex designs difficult. However, long tests and complex stimulus are required to put complex processors into interesting states where micro-architectural bugs are more readily found. With RISC-V processors and processing subsystems adding features including custom instructions to support high performance computing (HPC), AI, and automotive use cases among others, verification throughput becomes critical to achieving functional coverage closure. While running software for various use cases is a necessary piece of the verification plan, this does not sufficiently stress the Device Under Test (DUT) and drive it into corner cases. Micro-architectural features such as caches and complex memory transitions are very difficult to verify without long-running, synthetic tests. For example, the simple scenario of filling up a 4MB L3 cache using single byte memory operations needs more than 4 million instructions to execute. Bugs in these micro-architectural areas not only lead to functional issues but may also introduce security vulnerabilities.

Two problems then need to be solved. First, interesting and relevant tests need to be generated, and second, a high-performance test execution platform and environment is required to achieve higher verification throughput. This presentation describes a solution to these problems using the STING test generator and the ZeBu hardware emulation platform. Multiple obstacles were overcome in implementing this solution:

• Configuring and extending the test generator for the complex processors and subsystems of interest
• Integrating test generation with hardware emulation using a transactor, and optimizing the interface so that there is no time wasted between one test and the next, resulting in close to 5000x speedup in test execution as compared to RTL simulations
• Extending debug and functional coverage tools to work in this environment

Weihua Han is a Sr. Architect Application Engineer at Synopsys Protocol Solution Engineering team. Weihua graduated from Beijing University of Posts and Telecommunications with Master of Science degree. For more than 20 years Weihua has been working on different aspects of functional verification with simulation and HAV (hardware-assisted verification), using SystemC, SystemVerilog, UVM and PSS. Weihua is now focusing on RISC-V related functional verification solutions.