The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.
Event at a Glance
Thursday, 22 June 2023 – Full day conference, exhibition and networking event
Reading (UK) and online
FREE to attend conference In-Person or Online
REGISTER HERE
Call for Submissions
Abstracts are now being invited for talks at VF2023. Talks on a wide range of topical verification issues are invited, including, but not limited to; artificial intelligence and machine learning in verification, safety, security, software testing, and of course hardware verification.
Please visit VF2023 for guidance on the types of presentations that we are looking for.
Conference Program – Provisional
| 08:30 | Arrival: Breakfast and Networking | Slides | Videos |
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||
| Keynote Speakers | |||
| 09:30 | Functional safety for the world of Autonomous and Zonal Madhusudan Rao (Arm Ltd) |
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| User Top Verification Challenges | |||
| 10:15 | How to build the future verification engineers ? François Cerisier(AEDVICES) |
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| 10:30 | Application of AI in IC Design and Verification Matt Graham (Cadence Design Systems) Platinum Sponsor |
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| 11:00 | Refreshments and Networking | ||
| Multi-Track Session (AM) | |||
| Track 1 - User presentations on Verification Formal | |||
| 11:30 | The Power of Formal Verification: From flops to billion-gate designs Dr Ashish Darbari (Axiomise) |
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| 11:50 | Automatic Software Formal Verification Nick Tudor (D-RisQ Ltd) |
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| 12:10 | On Formally Verifying High-Level Synthesis Yann Herklotz (Imperial College London) |
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| Track 2 - Student Session 1 | |||
| 11:30 | Introduction to Verification and SystemVerilog for Beginners Dr David Long (Doulos) Gold Sponsor |
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| Track 3 - VHDL Verification | |||
| 11:30 |
Espen Tallaksen (EmLogic) |
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| 12:30 | Lunch and Networking | ||
| 13:30 | How does ChatGPT change ML in EDA Landscape? Ramesh Narayanaswamy (Synopsys Inc) Platinum sponsor |
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| 14:00 | Verification, bring-up, production – the wholly trinity Yiannis Nikolaou (Jump Trading International Ltd) Gold Sponsor |
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| 14:20 | RISC-V verification and implications of the 5:1 ratio of DV to design engineers Simon Davidmann (Imperas Software) Gold Sponsor |
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| 14:40 | How to sign-off cryptographic hash implementations with generated assertions Tobias Ludwig(LUBIS EDA) |
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| 15:00 | Refreshments and Networking | ||
| Multi-Track Session (PM) | |||
| Track 1 - Latest topics in Verification | |||
| 15:30 | Verification Makeover with RISC-V Processor Designs Lavanya Jagan (Vyoma Systems Private Limited) |
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| 15:50 | User experiences with open-source mainstream verification techniques Srinivasan Venkataramanan,Deepa Palaniappan (AsFigo Technologies) |
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| 16:10 | Closing Functional Coverage on A Compression Encoder with Deep Reinforcement Learning Eric Ohana(The University of Bielefeld, Germany) |
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| Track 2 - Student Session 2 | |||
| 15:30 | Is it easy to get started with UVM, or should I use Formal instead? Dr David Long (Doulos) Gold Sponsor |
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| Track 3 - VHDL Verification | |||
| 15:30 | Faster than “Lite” Verification Component Development with OSVVM Jim Lewis (SynthWorks Design Inc) |
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| Track 4 - UVM for AMS Verification | |||
| 15:30 | Renesas’s Submission to the UVM-(A)MS working group Peter Grove,Steven Holloway (Renesas) |
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| 16:30 | Event Closes |
Sponsors
VF2022 was made possible through the generosity of the following sponsors. If you would like to become a VF2022 sponsor please Contact Us.
