|Conference:||Verification Futures 2022 (click here to see full programme)|
|Presentation Title:||Enter the terrifying world of sim/synth mismatches|
|Abstract:||Are you sleeping well these days? Prepare to lose even more sleep after attending this session.
We verif engineers go to huge lengths to ensure that the RTL we deliver to the back end team is functionally correct, but does the RTL design we verify and deliver necessarily always match the design that is synthesized and used to make the chip out of?
This session will enter some of the scariest corners of the SystemVerilog LRM to expose where our RTL design simulations don’t match the silicon created from that RTL.
Forewarned is forearmed, so after reviewing potential problems we’ll also look at ways to expose whether we have hit the problems and ways to avoid them. Spoiler – the solutions are not all completely satisfactory.
If you get a frisson when you realise that no one has run the gate level sims and you’re trying to close verification then this session is for you.
|Speaker Bio:||Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore. At Imagination he was head of verification for the high-end GPU cores. At Graphcore his responsibilities include: leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT. Like all verif team leads at Graphcore he agonises about identifying and filling all verifications holes.|