|Verification Futures 2019 (click here to see full programme)
|Frank Schirrmeister, Cadence Design Systems
|Optimizing Verification Throughput a Connected World of 5G and AI/ML
|Verification Throughput has become the key challenge of today’s and next generation advanced verification required for Systems on Chips to be successful in a connected world. Users need to run as many cycles as possible in return for their tool and man-power investment. They need to employ smart verification practices to correct as many bugs as early as possible per dollar and day.
This keynote will outline the key challenges of 5G and AI/ML designs and introduce state of the art verification techniques to increase and scale bare performance of dynamic verification engines, explore how to smartly connect different levels of abstraction and introduce smart bug hunting techniques, allowing users to most efficiently use the verification cycles they spend.
|Frank Schirrmeister is senior group director for product management & marketing for emulation, virtual and FPGA based-prototyping and hardware/software enablement as part of the Cadence Verification Suite.
Prior to Cadence, Frank held senior leadership positions for product management, marketing and engineering at Synopsys, Imperas, ChipVision and SICAN Microelectronics. Frank graduated from the Technical University of Berlin.