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Co-simulation between C++ model for HPCs and an RTL emulator (Palladium z1)

Conference: Verification Futures 2019 (click here to see full programme)
Speaker: Luis Gutierrez, Cray
Presentation Title: Co-simulation between C++ model for HPCs and an RTL emulator (Palladium z1)
Abstract: Hardware emulator can provide greatly accelerated full-chip simulations, allowing for early software development and performance verification. However, they often come with hardware limitations. Here we explore and approach taken to virtualize PCI and network interfaces to allow for better use of the Hardware resources, and a more complete functional and performance verification
Speaker Bio: Luis has been involved in hardware verification and software testing for over 15 years. He started his career at Intel helping verify complex digital ASICs, AMS ASICs, moving onto pure logical CPUs later on; going into such diverse sectors as custom-verification ASICs, micro-controller CPUs, and GPUs and mobile phones.

He has worked on over 6 tape-outs for well know chip-makers, as well as startups, including Intel, NVIDIA and XMOS. Since 2014 has been at Cray, helping to verify the performance and integrity of the next-generation super computers; as well as developing their low-level software.

Luis gained an MSc in Microelectronics from the University of Southampton in 2003.

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