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Verification Challenges – Cadence Response

Conference: Verification Futures 2018 (click here to see full programme)
Speaker: Mike Stellfox, Fellow – System and Verification Solutions, Cadence
Presentation Title: Moving the Needle – Faster and Smarter Verification
Abstract: Most verification flows today consist of some combination of formal verification, simulation, emulation and FPGA based prototyping and these core engines continue to improve in terms of performance, capacity and memory footprint. Despite the expanded usage and technology advances in these core engines, the time, effort, and cost of verification continues to increase at an alarming rate. As if we didn’t have enough challenges already, with the industry focus and advances coming in Artificial Intelligence, Automotive, and Industrial Automation, many customers are facing significant challenges in new domains like Mixed Signal, Function Safety, and Security Verification. This presentation will explore where the next big advances in verification need to come in order to more effectively enable multi-engine, multi-domain verification flows.
Speaker Bio: Mike Stellfox leads the System and Verification Solutions Team at Cadence whose primary charter is to understand customer verification and software development challenges and to develop & deploy solutions to address those challenges. These methodology-based solutions span formal, simulation, emulation, and FPGA prototyping platforms. Mike has been working on solutions to advance the field of verification for the past 25 years, after starting his career at IBM as a chip designer.
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