The Art and Science of Automating Verification Checking

Conference: DVCLUB Europe | Automated Verification Checks
Speaker: Simon Davidmann, Imperas Software
Speaker Title: The Art and Science of Automating Verification Checking
Abstract: As with many aspects of modern verification plans, the methodologies and techniques are revised and improved over time to improve efficiency and quality. Specifications are the reference for all the key requirements from communication protocols, bus standards, and processor ISAs so these are the essential starting point. Automation starts with the specifications and supports the development of generators for coverage libraries, score boarding, event sequences, and test suites. Using examples from actual projects, this talk highlights the latest software generators for automating coverage tests.

Key Points:

  • Specifications are the basis of functional verification
  • Automating generators for coverage add efficiency and quality
  • How to apply software techniques to generators for SystemVerilog
Speaker Biography: Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) – the place for Fast Processor Models. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit, which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.

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