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Technology trends in Test

Conference: Tessolve Technology Symposium
Speaker: Yogan Senthilkumar
Presentation Title: Technology trends in Test

As the device Technology step in to Chiplets based solutions and Technology node shrinks to 3nm, there is an immense challenge on putting these device to production that will ensure , Test Coverage, Yield and COT. These challenges starts all the way from H.W development for Wafer, Package test till SLT. This short talk is on the changes in the approach to Test Technology for achieving the balance between DPPM, Yield and required COT budget.

Key Points

  • ATE H.W for Wafer and Package test complex increase as the Device pitch tends to go less than 0.5mm pitch.
  • Need for AI application at various stages of Test solution development.
  • Testing for customer-specific Use Case is becoming a key need for the devices that are used for mission-critical applications.
Speaker Biography:

He has 30 over years of experience in the field of Semiconductor Test. He is currently the Vice President Engineering @ Tessolve based out of Bangalore. He is with Tessolve from 2004. He has taken several roles that include Test engineering, R&D, H.W division.

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