|Tessolve Technology Symposium
|Technology trends in Test
As the device Technology step in to Chiplets based solutions and Technology node shrinks to 3nm, there is an immense challenge on putting these device to production that will ensure , Test Coverage, Yield and COT. These challenges starts all the way from H.W development for Wafer, Package test till SLT. This short talk is on the changes in the approach to Test Technology for achieving the balance between DPPM, Yield and required COT budget.
He has 30 over years of experience in the field of Semiconductor Test. He is currently the Vice President Engineering @ Tessolve based out of Bangalore. He is with Tessolve from 2004. He has taken several roles that include Test engineering, R&D, H.W division.