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SOC Verification in a Multi Chip Multi Die World

Conference: DVCLUB Europe | Performance Testing and Analysis
Speaker: Nick Heaton,Cadence design Systems
Speaker Title: SoC Verification in a Multi-chip, Multi-die world

Multi-core has pushed SoC integrators to go beyond basic testing; Coherency, Performance, Power, Security. With the commercial viability of multi-die SoCs there are now further challenges. This presentation touches on some of the biggest challenges facing the SoC Verification Engineer

Key Points:

  • Discuss the verification challenges posed by distributed cache from cluster, to interconnect to die-to-die.
  • How system performance as a concern is becoming a major problem.
  • What tools can help the verification engineer in state-of-the-art SoC verification?
Speaker Biography: Nick Heaton is an ASIC and EDA veteran with more than 30 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honors in Engineering and Management Systems, initially working as an ASIC designer for ICL in Bracknell. In 1993, he founded specialist ASIC Design and Verification Company Excel Consultants, servicing customers such as ARM® and Altera. In 2002, Nick joined Verisity (now Cadence) as Manager of Northern European Consulting Engineering.


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