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Best Conference Papers from 2022

Conference: DVCLUB Europe | Best Conference Papers from 2022
Speaker: Lukas Junger, MachineWare GmbH
Speaker Title: SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification

Over the last decades HW/SW software systems have become increasingly complex. Today, even small embedded systems are made up of different IP blocks from many vendors and execute complex software stacks consisting of millions of lines of code. This complexity ultimately leads to an increased risk of software bugs and security vulnerabilities that compromise the system’s security and safety. To detect these issues early in the design cycle, full system simulators based on the SystemC TLM-2.0 standard, so called Virtual Platforms (VPs), are the goto tool

Unfortunately, high target system complexity usually leads to reduced VP simulation performance. Contemporary VPs often fail to deliver the performance required for executing realistic workloads in a reasonable time frame. During target software development this is especially problematic as live software development requires close to real time feedback from the simulation. In Continuous Integration (CI) scenarios slow VPs prohibit testing of every commit and often only a daily CI run is possible, making it hard to pinpoint which exact change introduced faulty behavior.

To alleviate these problems we introduce SIM-V. SIM-V is a SystemC TLM-2.0 based RISC-V simulator targeted for early software development and verification. Its high-performance RISC-V processor models, based on our custom JIT engine FTL, enable the thorough verification of large target software stacks and by supporting several open integration layers, they can easily be integrated into existing VPs. In the presented case study, we show that SIM-V outperforms QEMU by a factor of 2x in both sequential and parallel execution, even though SIM-V has to carry the SystemC kernel and annotates timing information. Through integration with our open-source SystemC TLM-2.0 productivity library VCML, SIM-V offers Python scripting capabilities that enable deep introspection and instrumentation for seamless integration into complex CI scenarios.

Key Points:

  • Target hardware and software complexity induces the need for fast simulators for early software verification
  • Simulators will contain components from different vendors, thus standardisation for model interoperability is important
  • RISC-V is a new and fast moving, extendible ecosystem, where extensible and fast simulators are required
Speaker Biography: Lukas Jünger received his M.Sc. degree in Electrical Engineering from RWTH Aachen University. Afterwards he became a PhD student under the supervision of Prof.
Rainer Leupers at the Institute of Communication Technologies and Embedded Systems (ICE), where his research focus was on the acceleration of full system simulators for early target software development.
In 2022, he co-founded the ICE spin-off company MachineWare GmbH with the mission to bring novel ideas in simulation acceleration from university into industry especially focusing on instruction set simulation and RISC-V.


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