|Conference:||DVCLUB Europe | RISC-V Verification Strategies|
|Speaker:||Dr. Neel Gala, InCore Semiconductors Pvt. Ltd.|
|Speaker Title:||RISC-V Verif Generators : A Configurable ISA warrants a Configurable Verification Environment|
|Abstract:||First SW, then ISA, then HW and now its time for Verification to hop on the Open Source wagon as well. This talk will touch upon on various open source tools and environments that can be used to build a robust and scalable verification environement for RISC-V Cores with a primary focus on the following components:
– Test- Generation: Adapting to the configurability of RISC-V there is a huge shift towards generating tests rather than writing individual test suites. This section will discuss about various tools and schemes available to achieve both : ISA compliance and micro-architectural verification for any RISC-V Core.
– Scalable Test Harness: Leveraging CoCoTb framework to build a UVM compliant, and language & simulator agnostic test harness.Inherently enables step-n-compare methodology between the core and the reference model for more granular checks.
– Quality Metrics: Functional coverage is tough and its even worse if the design itself is configurable. Leveraging the OOPs and abstraction offered by Python, we see how configurable functional coverpoints can be defined using CoCoTb Coverage.Key Points:
|Speaker Biography:||Dr. Neel Gala is the CTO of InCore Semiconductors – an early stage fabless startup. Incore is one of the leading provider of silicon proven RISC-V processor IP in India. Dr. Neel received his PhD in Computer Science from IIT-Madras in 2016 and is also one of the creators of the SHAKTI Program initiated at IIT-Madras in 2012 . He was the lead architect of India’s first indigenously designed 64-bit RISC-V chip – codenamed RISECREEK. Dr. Neel also serves as the Vice-Chair of the Compliance Test Group of RISC-V International, published more than 20 international articles and an avid open-source contributor and promoter.|
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