|Conference:||DVCLUB Europe | RISC-V Verification Strategies|
|Speaker:||Simon Davidmann, Imperas Software|
|Speaker Title:||RISC-V processor verification with new open standard RVVI based methodology|
|Abstract:||RISC-V is extending the design freedoms for SoC developers with an open standard ISA. RISC-V is based on a modular framework with many standard extensions plus further optimization with custom instructions. SoC developers can explore the design flexibility as part of the growing trend for optimized domain specific processing. RISC-V is equally well suited to a range of workloads from embedded, to application processors and advanced AI compute requirements. In addition, RISC-V is adaptable for control functions and tasks in a multiprocessor system with supporting roles with communication protocols, plus power and security management.
Now all SoC design verification plans will need to cover the complexity of a custom processor implementation, or perhaps multiple different processors as part of a multiprocessor with arrays of heterogeneous cores. DV teams will need to adapt to include processor verification requirements, which highlights the impact not just on individual designs but the emerging RISC V Verification Ecosystem that supports all adopters.
This talk outlines RVVI (RISC-V Verification Interface), a new open standard interface for RISC-V verification including the integration methodology for the processor RTL (DuT) and reference model within a unified SystemVerilog testbench. It discusses a range of approaches based on the verification test plan needs for proof-of-concept test chips or research projects, to high reliability application and high-volume silicon production. RVVI also address the complexity of the functional verification for superscalar, out-of-order, multi-hart, multi-thread, vector accelerators, privileged and debug modes of operation. Together these guidelines help to adapt the current industry standard SoC verification methods for RISC-V processor DV, and establish a common framework that supports reuse and shared contributions across the whole DV community.
As more SoC developers embrace the design flexibility and potential of RISC-V, the overall verification efficiency will play an increasing important role in project planning and time-to-market schedules. The efficiency of the DV flow from issue identification to resolution is a key factor in reducing both the risk in time schedules and the consequences with late-stage bug detection.
This talk highlights the experience in using an RVVI based methodology for the testing of a popular series of open-source IP cores, and guidance for implementing RVVI for new processor DV projects.
|Speaker Biography:||Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) – the place for Fast Processor Models. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit, which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.|
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