|DVCLUB Europe | Using AI/ML in Design Verification
|Lokesh Babu Pundreeka, Cadence Design Systems
|Navigating the verification Complexity with Cadence AI-ML
The Cadence Verisium Artificial Intelligence (AI)-Driven Platform represents a generational shift from single-run, single-engine algorithms to algorithms that leverage big data and generative AI across multiple runs of multiple engines throughout an entire SoC verification campaign. The Verisium platform optimizes verification workloads, boosts coverage, and accelerates root cause analysis of bugs. It is built on the Cadence Joint Enterprise Data and AI (JedAI) Platform, enabling Cadence to unify its computational software innovations in data and AI across the full portfolio of Cadence products and solutions. Presentation will provide over view of cadence AI-ML solutions like verisium, Jasper and Xcelium and how they are scaling to address complex verification challenges.
Astute Design and Verification Leader with over 2 decades of experience in digital hardware design and verification with an unmatched prowess in project management skills, EDA, ASIC, IP, SOC, Front-end Design, ARM, ABV, Low Power, Formal Verification, Emulation and Automotive-Functional Safety (ISO 26262), identifying process improvements in IC verification with expertise in front-end. Expertly direct the planning and execution of multiple cross-culture projects and programs, leading both local and virtual teams. Implement standardized project management methodologies, cost controls, and best practices; prioritize resources, and develop creative solutions to broad issues. Combine client-focused mindset with strong technical acumen to achieve timely delivery of high-quality products, services, and support. Adept at optimal utilization of teams, processes, and technology.
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