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Generation of Functional Coverage for RISC-V Processor Verification

Conference: DVCLUB Europe | Auto-generation of Verification Infrastructure for IP to SoC
Speaker: Larry Lapides, Imperas Software Ltd.
Speaker Title: Generation of Functional Coverage for RISC-V Processor Verification

The open standard RISC-V instruction set architecture (ISA) offers developers new freedoms and flexibilities to develop domain-specific processors. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies that SoC design verification teams will need to address the challenge and complexity of processor verification.

A key metric for design verification (DV) is functional coverage. Given the number of extensions in the RISC-V ISA, and instructions per extension, just writing the functional coverage modules is challenging. With over 1,000 instructions in the ISA, functional coverage for a fully featured processor could require > 100,000 lines of SystemVerilog.

. Writing this by hand is certinaly time-consuming and resource intensive, and is vulnerable to errors. We report here on a methodology for auto-generation of the functional coverage modules for RISC-V processor DV. This presentation will put the functional coverage requirement and use in the context of the DV methodology, and show examples of not just functional coverage of instructions but also of other architectural features such as MMU.

Key Points:

  • RISC-V processors need to be verified
  • Functional coverage is a key verification metric
  • Imperas riscvISACOV is automatically generated SystemVerilog functional coverage
Speaker Biography:

Larry is currently VP Sales & Marketing at Imperas Software Ltd., and previously ran worldwide sales at EDA companies Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001 in the U.S.), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Prior to moving into marketing and sales, Larry spent 9 years working on infrared photodiode design and fabrication.

Larry has been on the Clark University Graduate School of Management (GSOM) Advisory Council since 2003, and was an Entrepreneur-in-Residence at Clark during Fall 2006, when he developed and taught the course on Entrepreneurial Communication and Influence.

Larry holds a BA in Physics, with General Distinction and Honors in Physics, from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University.


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