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Conference: DVCLUB Europe | Auto-generation of Verification Infrastructure for IP to SoC
Speaker: Simon Davidmann, Imperas Software
Speaker Title: Generation and Configuration of Functional Coverage and Verification IP for RISC-V Processor Verification

The open standard RISC-V instruction set architecture (ISA) offers developers new freedoms and flexibilities to develop domain-specific processors. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies that SoC design verification teams will need to address the challenge and complexity of processor verification.

A key metric for design verification (DV) is functional coverage. Given the number of extensions in the RISC-V ISA, and instructions per extension, just writing the functional coverage modules is challenging. With over 1,000 instructions in the ISA, functional coverage for a fully featured processor could require > 100,000 lines of SystemVerilog. Writing this by hand is certainly time-consuming and resource intensive, and is vulnerable to errors. We report here on a methodology for auto-generation of the functional coverage modules for RISC-V processor DV.

Auto-generation and auto-configuration of verification IP.

This presentation will put the functional coverage requirement and use in the context of the DV methodology, and show examples of not just functional coverage of instructions but also of other architectural features such as MMU

Key Points:

  • RISC-V processors need to be verified
  • Functional coverage is a key verification metric
  • Imperas riscvISACOV is automatically generated SystemVerilog functional coverage
Speaker Biography:

Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms ( - the place for Fast Processor Models. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co Design Automation, the developer of SystemVerilog. Prior to founding Co Design Automation, Simon was an executive or European GM with 5 US based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit, which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.


DVCLUB Europe is made possible through the generosity of our sponsors.

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