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Formal Verification with AI/ML

Conference: DVCLUB Europe | Formal Verification
Speaker: Gayatri Padhy, Object Automation
Speaker Title: Formal Verification with AI/ML

Formal verification plays a crucial role in chip design as it helps identify and eliminate design errors and bugs before fabrication. It provides a rigorous and systematic approach to ensure the reliability, safety, and correctness of digital designs.

Key Points:

  • Time & Resource Efficiency
  • Error Discovery & Correction
  • Complexity Management
Speaker Biography:

Gayatri Padhy is an esteemed speaker known for her profound insights techniques into formal verification development methods and AI/ML use in VLSI Design. With an experience in Verification background and Design studies, Gayatri brings a unique perspective to her presentations, blending all techniques.


DVCLUB Europe is made possible through the generosity of our sponsors.

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