Cadence will present how to create FMEDA at the architectural level, and how to refine for detailed design level. We will show the steps to create the fault list to drive the fault simulation campaign, reducing the fault list, and correctly classifying faults. We will explain how the fault campaign is managed and how Diagnostic Coverage (DC) is measured and fed back to FMEDA to show the relevant ASIL fault metrics can be met.

Key Points:

• Integrated FMEDA is important to drive the safety verification flow with the easiest path to certification.
• Even with high-performance fault simulation, techniques to reduce the fault list as much as possible remain important.
• Fault emulation allows the correct system software reaction to faults to be validated.

Pete Hardee is Product Management Group Director for the System and Verification Group (SVG) at Cadence Design Systems. He is responsible for the Jasper formal verification product line as well as SVG’s security and functional safety solutions.

Hardee joined the EDA industry in 1994 and, prior to joining Cadence in early 2010, has worked in various technical, marketing and sales roles at Synopsys and CoWare. Prior to EDA, Pete’s design background was mainly in safety-critical systems in the Aerospace industry. He holds a bachelor’s degree in electrical engineering from Imperial College, London, and an MBA from Warwick Business School.