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CORE-V-VERIF: an open-source SV/UVM environment for RISC-V cores

Conference: DVCLUB Europe | RISC-V Verification Strategies
Speaker: Mike Thompson, OpenHW Group
Speaker Title: CORE-V-VERIF: an open-source SV/UVM environment for RISC-V cores
Abstract: CORE-V-VERIF is an open-source project supported by the OpenHW Group. Its goal is to provide an open-source environment and work-flow that can be deployed onto any RISC-V processor core. In December of 2020, OpenHW Group members successfully use CORE-V-VERIF to complete the end-to-end verification of the CV32E40P CORE-V core, a RISC-V compatible RV32IMC core.To date, CORE-V-VERIF has been deployed on six RISC-V cores.

Key Points:

  • CORE-V-VERIF is an open-source SV/UVM environment for RISC-V cores.
  • OpenHW applies industry leading tools and methodologies to fully verify its open-source RTL IP.
  • CORE-V-VERIF can be used as-is, or by using select components such an Instruction Stream Generator, UVM Bus Agents, Assertion Libraries and Functional Coverage.
Speaker Biography: Mike is a functional verification engineer and manager who has been involved in all aspects of the discipline: simulation, emulation, prototyping and formal verification. He is strong proponent of coverage driven processes in the pursuit of first-time-right silicon.


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