|Conference:||DVCLUB Europe | Automated Verification Checks|
|Speaker:||David Kelf, Breker Verification Systems|
|Speaker Title:||Automating Checks Through Executable Specification Synthesis|
Composing checks for block and system designs is one of the most onerous and error-prone verification tasks. The automation of scoreboards and reference models is now possible through the use of test content synthesis. Self-checking tests, along with stimulus and coverage models, may be derived from a specification model based on the Accellera Portable Stimulus standard or C++, augmenting existing reference models or generating checks from scratch. This approach brings to life the notion of the executable specification, allowing an automated path from a readable spec to test content that can be used in existing UVM testbenches, on SoC sub-systems and with full, software-driven system tests.Key Points:
|Speaker Biography:||David Kelf, is the Chief Executive Officer at Breker Verification Systems and has been with the company four years as CEO and formerly in the VP Marketing role. Previous to Breker, Dave most recently served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier, Kelf was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys.
Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.
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