Abishaan Ravikumar (Oxford Brookes University and Infineon Technologies )

Integrated Circuit (IC) verification, i.e. the process of ensuring that it performs according to the design specifications, is highly resource intensive. This often depends on an IC’s complexity, e.g. the number of gates/transistors which translates into expressions, branches, blocks, etc in its high-level descriptions. To reduce overall verification and hence design time, industries resort to “Regression Testing” where a very small test suite, with very high-test coverage, is selected to verify any modified design block and its dependencies. One of the key steps in regression test-based verification is distributing the tests to the various interconnected blocks under tests based on their functionality and accessibility, which translates into a block's “connection strengths'' among other parameters. The existing approaches currently define the connection strengths manually by the design experts which often lead to inconsistency in the test results. In this paper, we propose a Graph Neural Network (GNN) based approach to estimate the connection strengths of different interconnected blocks and evaluate its effectiveness with industrial designs in conjunction with a technique called ``SMART Regression" compared to random and full regression testing.

Key Points:

• IC design verification
• Test Selection
• Regression

Abishaan is a third-year PhD student at Oxford Brookes University, specializing in Integrated Circuit (IC) verification. Working on optimizing test selection methodologies to enhance verification efficiency, leveraging machine learning and graph-based techniques. Collaborating with Infineon Technologies, they aim to develop novel approaches for circuit validation, ensuring robust and high coverage testing strategies.

With a background in software engineering and quality engineering, Abishaan has published research papers on AI-driven verification techniques and continues to explore the intersection of AI and IC verification. Their work contributes to advancing automated verification methods, reducing time-to-market for complex IC designs.